1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular, to an apparatus and method for programming a non-volatile memory device which is electrically erasable and programmable.
2. Description of the Related Art
Semiconductor memory devices are largely divided into RAMs (Random Access Memories) and ROMs (Read-Only Memories). RAMs are of various types such as DRAMs (Dynamic RAMs) and SRAMs (Static RAMs). RAMs are referred to as volatile memories since data stored in them is destroyed with passage of time. RAMs also allow rapid data storage and data retrieval. In contrast, ROMs retain data once it is entered but perform slow data storage and data retrieval. Among the various types of ROMs, demand for flash EEPROMs (Electrically Erasable and Programmable ROMs), in which data is electrically input and output, is increasing. A flash EEPROM device, which is electrically erasable at high speed without being removed from a circuit board, offers the advantages of simple memory cell structure, low cost per unit memory, and no need for a refresh function to retain data.
Flash EEPROM cells can be of two types, namely, a NOR type and a NAND type. The NOR type is not readily applicable to realization in high integration because one contact is required for every two cells. However, the NOR-type is useful for high-speed operation due to a high cell current. On the contrary, the NAND-type flash EEPROM can be packed on a chip with high density because a plurality of cells share one contact, though its low cell current impedes high-speed operation. Therefore, the NAND flash EEPROM device is receiving considerable attention as a next generation memory device for use in a digital still camera and similar devices.
FIGS. 1 and 2 contain a schematic sectional view and a schematic equivalent circuit diagram, respectively, of a cell array in a conventional NAND flash EEPROM device, as disclosed in, for example, in an article entitled, "A 4-Mbit NAND-EEPROM with Tight Programmed Vt Distribution," in 1990 Symposium on VLSI Circuits, pp. 105-106, 1990. Referring to FIGS. 1 and 2, a string of the NAND flash EEPROM cell array includes a string select transistor (SST) for selecting a unit string, a ground select transistor (GST) for selecting a ground, and a plurality of memory cell transistors MC1, . . . , and MC16 connected in series between the SST and the GST, each being stacked with a floating gate 18 and a control gate 21. One block has a plurality of such strings connected in parallel to bit lines B/L1, B/L2, . . . , and blocks are symmetrically arranged with respect to a bit line contact.
The transistors are arranged in a matrix of rows and columns. The gates of SSTs and GSTs in the same rows are connected to a string select line (SSL) and a ground select line (GSL), respectively, and the gates of memory cell transistors MC1, . . . , and MC16 in the same rows are connected to their respective corresponding word lines W/L1, . . . , and W/L16. The drain of the SST is coupled to a bit line B/L, and the source of the GST is coupled to a common source line (CSL).
In each of the memory cell transistors MC1, . . . , and MC16, the floating gate 18 is formed on a semiconductor substrate 10 with interposition of a tunnel oxide film 16, and the control gate 21 is stacked over the floating gate 18 with interposition of an interpoly dielectric layer 19. The floating gate 18 extends across an active region and portions of edges of field regions at opposite sides of the active region, thus being isolated from a floating gate 18 of an adjacent cell. The control gate 21 is connected to that of an adjacent cell, forming a word line W/L.
The floating gate 18 and the control gate 21 are coupled by a metal line through a butting contact on a field region of the cell array, in SSTs and GSTs, because they require no floating gates for storing data. Hence, the SSTs and GSTs operate as MOS transistors having a single layer gate structure in electrical terms.
The operation of such a NAND flash EEPROM cell will now be described. For a programming operation of the cell, electrons are injected from a channel region into a floating gate by Fowler-Nordheim (F-N) tunneling due to a large voltage difference between the channel region and a control gate of the cell transistor by applying 0 V and a program voltage Vpgm to a bit line and a word line connected to the selected cell transistor, respectively. During the operation, a pass voltage Vpass is applied to word lines connected to unselected cell transistors among a plurality of memory cells between the bit line and a ground node, to pass the data (i.e, 0 V) of the selected bit line to the selected cell transistor. Here, the threshold voltage of the cell transistor shifts to a positive voltage.
An erasing operation refers to removal of electrons from the floating gate. By applying an erase voltage Verase of about 20 V to a bulk and 0 V to the word line connected to the selected cell transistor, the electrons stored in the floating gate are replaced with holes due to an erase voltage-induced electric field directed opposite to that in the programming operation. During erasing, the initial threshold voltage of the cell transistor is about -3 V.
Reading of the cell is achieved by determining its data as "0" or "1 " depending on the absence or presence of a current path through the selected cell transistor by applying 0 V to the selected word line, based on the principle that the threshold voltage Vth of the cell shifts to +1 V with electrons stored in the cell transistor and to -3 V with holes stored therein.
The programming of the cell is implemented following the erasing operation of all cell transistors, and unselected cell transistors should be inhibited from being programmed in order to prevent program disturbance of an unselected cell transistor connected to an unselected bit line of the selected word line during programming. A conventional program inhibition method utilizing a self-boosting scheme is provided by JSSC (Journal of Solid State Circuits), Vol. 30, No. 11, pp. 1149-1156, 1995 and will be described in connection with its circuit diagram in FIG. 3.
Referring to FIG. 3, to program cell A, for example, a ground path is blocked in the memory cell array by applying 0 V to the gate of a GST or a GSL. 0 V is applied to a selected bit line, and a power supply voltage Vcc of 3.3 V or 5 V is applied as a program inhibition voltage Vpi to unselected bit lines. At the same time, after the source of an SST is charged to (Vcc-threshold voltage SST.sub.Vth of SST) by applying the power supply voltage Vcc to the gate of the SST or an SSL, the SST is virtually blocked. The channel regions of cell transistors in the same string are charged to (Vcc-SST.sub.Vth)/17 by charge sharing in the case of a 16-stage NAND type, by applying a program voltage Vpgm of about 18 V to a selected word line and a pass voltage Vpass of about 10 V to unselected word lines. By passing voltages applied to the selected word line, a channel voltage Vch of cell transistors is given as follows due to capacitive coupling caused by the high program voltage Vpgm on the selected word line: ##EQU1## where Cch is a depletion capacitance generated by a depletion region under a channel and Cins is a total capacitance between a control gate and the channel.
Assuming that the program voltage Vpgm is 20 V and the pass voltage Vpass is 10 V, about 8 V is induced to the channel region of a program inhibited cell transistor. Then, F-N tunneling cannot take place between the floating gate and the channel, thereby keeping the program inhibited cell transistor in the initial erased state, that is, at a threshold voltage of -3 V.
In the conventional method, however, if the power voltage Vcc drops, the value [(Vcc-SST.sub.Vth)/17+Vboost] also drops, and the potential difference between the channel voltage Vch of the program inhibited cell transistor and the program voltage Vpgm on the selected word line becomes large. As a result, soft-programming (hereinafter, referred to as Vpgm stress), caused by the program voltage Vpgm on the control gate of the selected cell transistor, becomes serious, and the program inhibited cell transistor is not kept at its initial erased status and has an increased threshold voltage. Moreover, unselected cell transistors in a string receiving 0 V on its bit line are subjected to soft-programming (hereinafter, referred to as Vpass stress) due to an increased voltage difference between their control gates and channels as the pass voltage Vpass is increased. As a result, their threshold voltages are increased. Therefore, an optimum pass voltage Vpass should be determined in a pass voltage range free of Vpgm and Vpass stresses.
FIG. 4 is a graph illustrating variation of a threshold voltage Vth of a program inhibited cell with respect to a pass voltage Vpass thereof with a program voltage Vpgm of 17 V, a total program stress time Tpgm of 3 ms, and a program inhibition voltage Vpi varied from 2.8 V through 3.8 V to 5 V in the conventional method. It is noted from FIG. 4 that the window of a pass voltage range free of Vpgm and Vpass stresses is gradually reduced with the decrease in the program inhibition voltage Vcc on a bit line.
Another problem with the conventional method is that a program disturbance window is decreased because of a programming time increased by three or more times and a program voltage increased by 3 V or higher during operation of a multi-bit NAND flash memory cell for recording two or more bit data per cell.
Another conventional program inhibition method relying on local self-boosting (LSB) to overcome the above conventional problems, disclosed in ISSCC Digest of Technical Papers, pp. 32-33, 1996, will be described referring to FIG. 5. Referring to FIG. 5, a decouple voltage Vdecouple of 0 V is applied to two unselected word lines adjacent to a selected word line. About 2 .mu.s after a pass voltage Vpass of about 10 V is applied to the other unselected word lines, the program voltage Vpgm of about 18 V is applied to the selected word line. Then, the channel of a self-boosted cell transistor is confined to the selected word line and the boosting voltage Vboost is increased, resulting in improvement of Vpgm stress. According to the LSB method, the channel voltage Vch of a program inhibited cell transistor is calculated by ##EQU2## and ##EQU3## Thus, Vpgm stress is more improved than in the program inhibition method using self-boosting described referring to FIG. 3.
FIG. 6 is a graph illustrating variation of a threshold voltage Vth of a program inhibited cell with respect to a pass voltage Vpass thereof, with the threshold voltage of a cell transistor receiving a decouple voltage varied from -5 V through -3 V to -1 V. Here, a program voltage Vpgm is 20 V, a total program stress time Tpgm is 2.4 ms, and a program inhibition voltage Vpi is 2.8 V.
Referring to FIG. 6, as the voltage Vcc on a bit line for program inhibition drops, the window of a pass voltage range free of Vpgm and Vpass stresses is improved by 3 V or higher, as compared to the conventional method shown in FIG. 4. However, when the initial threshold voltages of two cell transistors receiving the decouple voltage Vdecouple are overerased, the channel of a self-boosted cell transistor is not confined to a selected word line. Hence, as shown in FIG. 6, Vpgm stress increases and the threshold voltage varies to a large extent. In addition, if the initial threshold voltages of the two cell transistors receiving the decouple voltage Vdecouple are undererased, the voltage (Vcc-SST.sub.Vth) to which the source of an SST is precharged fails to be substantially transported to the channel of a program inhibited cell. In the worst case where a cell transistor on the selected word line is programmed, the channel of the program inhibited cell transistor is precharged to [(Vdecouple(0 V)-Vth of cell transistor receiving Vdecouple)/17)]. Therefore, since the difference between the potentials of the channel voltage Vch of the program inhibited cell transistor and the program voltage Vpgm on the selected word line becomes large, Vpgm stress increases and the threshold voltage varies to a large extent, as shown in FIG. 6.